HLDVT 2007 - Call for Participation

CALL FOR PARTICIPATION

Overview -- Registration -- Hotel -- Advance Program -- Additional Information -- Committees

Overview

IEEE International High Level Design Validation and Test Workshop aims to stimulate research in test and validation methodologies for ICs and systems specified using high level descriptions, where high level refers to register-transfer, behavioral, and system level. The goal of the workshop is to provide an informal forum, bringing together designers and test and verification researchers working in validating, debugging, synthesizing, and testing designs specified using high level descriptions, in an effort to address high level design, validation, and test issues concurrently.

Registration

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Please visit http://www.hldvt.com/07/registration.html for registration.

Advance registration deadline: October 11, 2007

Hotel

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Please visit http://www.hldvt.com/07/local.html for hotel information and registration.

Deadline to secure discounted rates: October 24, 2007

Advance Program

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Wednesday -- Thursday -- Friday

November 7, 2007 (Wednesday)

6:00 PM - 8:00 PM	Registration

November 8, 2007 (Thursday)

7:00 AM - 8:00 AM	Continental Breakfast

7:00 AM - 5:00 PM	Registration

7:50 AM - 8:00 AM	Welcome

8:00 AM - 8:50 AM	Session 1: Network-on-Chip Session Chair: TBD
	*Reliable Network-on-Chip Based on Generalized de Bruijn Graph* Mohammad Hosseinabady, Univ. of Bristol; Mohammad Reza Kakoee, Univ. of Tehran; Jimson Mathew, and Dhiraj Pradhan, Univ. of Bristol
	*A New Efficient Routing Algorithm for Network-on-Chip with Best Input and Output Selection Techniques* Ebrahim Behrouzian Nezjad, Ahmad Kadem Zadeh, Azad Univ. of Iran

8:50 AM - 9:10 AM	Break

9:10 AM - 10:50 AM	Session 2: Multiprocessor Systems Session Chair: Robert Jones, Intel Corp.
	*Improving Feasible Interactions Among Multiple Processes* Kiran Ramineni, Ian Harris and Shireesh Verma, Univ. of California, Irvine
	*Framework for Fast and Accurate Performance Simulation of Multiprocessor Systems* Eric Cheung, Harry Hsieh, Univ. of California, Riverside, and Felice Balarin, Cadence Design Systems, Inc.
	*Automatic TLM Generation for C-Based MPSoC Design* Lochi Yu, Samar Abdi, Univ. of California, Irvine
	*Automatic Buffer Sizing for Rate-Constrained KPN Applications on Multiprocessor System-on-Chip* Eric Cheung, Harry Hsieh, Univ. of California, Riverside, and Felice Balarin, Cadence Design Systems, Inc.

10:50 AM - 11:10 AM	Break

11:10 AM - 12:25 PM	Session 3: Invited Session: Post-Silicon Validation Session Chair: Allon Adir, IBM Corp.
	*Post-Silicon Verification Methodology on Sun’s UltraSPARC T2* Jai Kumar, Catherine Ahlschlager, Peter Isberg, SUN Microsystems
	*Post-Silicon Verification of IBM’s Game Chips* Shakti Kapoor, IBM Corp.
	*Intel’s Post-Silicon Validation Approach* Tommy Bojan, Intel Corp.

12:25 PM - 2:00 PM	Lunch

2:00 PM - 3:15 PM	Session 4: Debug Session Chair: Prabhat Mishra, Univ. of Florida
	Bug Analysis and Corresponding Error Models in Real Designs Tao Lv, Tung Xu, Yang Zhao, Hua-wei Li, Xiao-wei Li, Chinese Academy of Sciences
	Automatic Error Diagnosis and Correction for RTL Designs Kai-hui Chang, Ilya Wagner, Valeria Bertacco, Igor Markov, Univ. of Michigan
	Bridging RTL and Gate: Correlating Different Levels of Abstraction for Design Debugging Eric Cheung, Univ. of California, Riverside, Xi Chen, Furshing Tsai, Yu-Chin Hsu, Novas Software, Inc., Harry Hsieh, Univ. of California, Riverside

3:15 PM - 3:30 PM	Break

3:30 PM - 4:45 PM	Session 5: Test Generation Session Chair: Miroslav Velev, Consultant, USA
	*Model-driven Test Generation for System Level Validation* Deepak Mathaikutty, Sumit Ahuja, Sandeep Shukla, Virginia Tech., Ajit Dingankar, Intel Corp.
	Towards RTL Test Generation from SystemC TLM Specifications Mingsong Chen, Prabhat Mishra, Univ. of Florida, Dhrubajyoti Kalita, Intel Corp.
	*A Novel Formal Approach to Generate High-level Test Vectors without ILP and SAT Solvers* Bijan Alizadeh, Masahiro Fujita, Univ. of Tokyo

6:00 PM - 8:00 PM	Banquet Dinner
	Keynote: John Barton, General Manager, Platform Validation Engineering, Digital Enterprise Group, Intel Corp.

November 9, 2007 (Friday)

7:00 AM - 8:00 AM	Continental Breakfast

7:00 AM - 12:00 Noon	Registration

8:00 AM - 9:15 AM	Session 6: Formal Verification Session Chair: Rupak Majumdar, UCLA
	*Hierarchical Cache Coherence Protocol Verification One Level at a Time Through Assume Guarantee* Xiaofang Chen, Yu Yang, Michael Delisi, Ganesh Gopalakrishnan, Univ. of Utah, Ching-Tsun Chou, Intel Corp.
	*Formal Model Construction Using HDL Simulation Semantics* Joseph Buck, Dong Wang, Synopsys, Inc., Yunshan Zhu, Independent Consultant
	A New Approach for Computing the Initial State for Retimed Synchronous Sequential Circuits Noureddine Chabini, Royal Military College of Canada, Wayne Wolf, Princeton Univ., Georgia Institute of Technology

9:15 AM - 9:35 AM	Break

9:35 AM - 10:50 AM	Session 7: Invited Session: High Level Design Session Chair: Michael Kishinevsky, Intel Corp.
	*High-Level Modeling, Design, Verification, and Synthesis of Circuits with Esterel* Gerard Berry, Esterel Technologies
	FFT Compiler: From Math to Efficient Hardware James Hoe, Carnegie Mellon Univ.
	*Transactors for Parallel Software and Hardware Codesign* Krste Asanovic, Univ. of California, Berkeley

10:50 AM - 11:10 AM	Break

11:10 AM - 12:25 PM	Session 8: Coverage Directed Validation Session Chair: TBD
	*Functional Coverage Measurements and Results in Post-Silicon Validation of Core™2 Duo Family* Tommy Bojan, Manuel Aguilar, Eran Shlomo, Tal Shachar, Intel Corp.
	*Coverage-Directed Test Generation through Automatic Constraint Extraction* Onur Guzey, Li-C. Wang, Univ. of California, Santa Barbara
	*Automatic Generation of Functional Coverage Models from CTL* Shireesh Verma, Ian Harris, Kiran Ramineni, Univ. of California, Irvine

12:25 PM - 2:00 PM	Lunch

2:00 PM - 3:30 PM	Session 9: Panel: Unified Test Bench for All Phases of a Multi-Core Design, Validation and Production Test – How to Get There? Moderator: Sunil Kakkar, Qualcomm
	Panelists: Brian Bailey, Independent Consultant, Harry Foster, Mentor Graphics Corp., Ian Harris, Univ. of California, Irvine, Janick Bergeron, Synopsys, Inc.

3:30 PM - 3:45 PM	Break

3:45 PM - 5:00 PM	Session 10: Embedded Systems Session Chair: Rajesh Gupta, Univ. of California, San Diego
	*Automating the IEEE std. 1500 Compliance Verification for Embedded Cores* Alfredo Benso, Politecnico di Torino, Alberto Bosio, Univ. de Montpellier, Stefano Di Carlo, Paolo Prinetto, Politecnico di Torino
	*Validating the Dependability of Embedded Systems through Fault Injection by Means of Loadable Kernel Modules* Marco Murciano, Massimo Violante, Politecnico di Torino
	*AME: An Abstract Middleware Environment for Validating Networked Embedded Systems Applications* Giovanni Perbellini, Franco Fummi, Davide Quaglia, Sara Vinco, Univ. of Verona

Additional Information

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General Information

Michael Hsiao
General Chair
E-mail: generalchair@hldvt.com

Committees

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General Chair
Michael Hsiao, Virginia Tech

Program Chair
Yatin Hoskote, Intel

Past Chair
Robert Jones, Intel

Finance Chair
Priyank Kalla, Univ. of Utah

Publicity Chair
Ismet Bayraktaroglu, Sun

Local Arrangements Chair
Vijay Nagasamy, NEC Electronics

Program Committee
Mark Aagaard, Univ. of Waterloo
Samar Abdi, UC Irvine
Jacob Abraham, Univ. of Texas
Hussain Al-Asaad, UC Davis
Felice Balarin, Cadence Berkeley Labs
Valeria Bertacco, Univ. of Michigan
Tim Cheng, UC Santa Barbara
Scott Davidson, Sun
Farzan Fallah, Fujitsu Labs of America
Franco Fummi, Univ. di Verona
Kiyoharu Hamaguchi, Osaka Univ.
Ian Harris, UC Irvine
John Hayes, Univ. of Michigan
Harry Hsieh, UC Riverside
Alan Hu, Univ. British Columbia
Michael Kishinevsky, Intel
Ed McCluskey, Stanford Univ.
Alex Orailoglu, UC San Diego
Wolfgang Rosenstiel, Tubingen Univ.
Pablo Sanchez, Univ. of Cantabria
Sandeep Shukla, Virginia Tech
Lionel Torres, Univ. of Montpellier
Li-C.Wang, UC Santa Barbara
Jin Yang, Intel
Avi Ziv, IBM

Steering Committee
Bernard Courtois, CMP-TIMA
Sujit Dey, UC San Diego
Masahiro Fujita, Univ. of Tokyo
Prab Varma, Blue Pearl Software

For more information, visit us on the web at: http://www.hldvt.com/07

The IEEE International High-Level Design, Validation and Test Workshop (HLDVT'07 ) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee. HLDVT 2007 receives corporate support from IBM.